The present invention relates generally to integrated circuit (IC) designs, and, more particularly, to voltage level shifter designs.
As semiconductor feature sizes scale down to a deep submicron region, their operation voltages also have to scale down. For instance, in a 65 nm process technology, the operation voltage is around 1.0V. But outside such a chip, i.e., in the system level, the operation voltage may still remain, for example, 1.8V. Then a need for voltage level shifters arises. A high-to-low voltage level shifter transfers input signals from 1.8V to 1.0V for chip internal operations. A low-to-high voltage level shifter transfers output signals from 1.0V to 1.8V for system operations.
A conventional voltage level shifter employs two stage complementary metal-oxide-semiconductor (CMOS) circuits, with a first stage operating at a first voltage, and a second stage operating at a second voltage. When their threshold voltages are properly adjusted, they can perform voltage level shifting as desired.
However, the conventional voltage level shifter may occupy large layout areas. Because a first Nwell for a P-type metal-oxide-semiconductor (PMOS) transistor in the first stage is coupled to a first voltage, while a second Nwell for a PMOS transistor in the second state inverter is coupled to a second voltage, therefore, the first and second Nwells have to be separated and have to maintain a certain distance, which is determined by the technology being used. Two separated Nwells certainly occupy a larger layout area than a single Nwell.
As such, what is desired is a voltage level shifter with a Nwell coupled to a single voltage, and hence both first and second PMOS transistors may be formed in a single Nwell.